1. Field of the Invention
The present invention relates to a MOS FET (MOS type field effect transistor) having an LDD (lightly doped drain) structure.
2. Description of the Related Art
It is known to the art that an LDD structure is effective for preventing a change of characteristics caused by hot carriers in an n-channel type MOS FET.
FIG. 1 is a cross sectional view showing the construction of a conventional n-channel type MOS FET utilizing an LDD structure. As shown in the drawing, a gate electrode 3 is formed on a p-type silicon substrate 1 with a gate oxide film 2 having a thickness of, for example, 150 .ANG. interposed therebetween. Source and drain regions are formed apart from each other on the substrate with the gate electrode 3 positioned therebetween. Each of these source and drain regions comprises an n.sup.- -type region 4 containing a low concentration of an n-type impurity and an n.sup.+ -type region 6 containing a high concentration of an n-type impurity. The n.sup.- -type region 4, which is positioned on the substrate surface, is formed by means of an ion implantation using the gate electrode 3 as a mask. On the other hand, the n.sup.+ -type region 6 is formed by an ion implantation using as a mask the gate electrode 3 and an oxide film 5 covering the side surface of the electrode 3.
In the LDD structure shown in FIG. 1, the n.sup.- -type region 4 on the side of the drain region serves to moderate the peak intensity of the electric field in the drain depletion layer even if a high voltage is applied to the drain side, as described in S. Ogura et al., IEEE Trans. Electron Devices, "Design and characteristics of the lightly doped drain-source (LDD) insulated gate field effect transistor" ED-27, P.1359 (1980). As a result, an impact ionization of hot carriers in the vicinity of the drain region is suppressed so as to decrease the generation of new carriers and, thus, to achieve a high reliability even under application of a high voltage.
It should also be noted that the oxide film 5 left unremoved on the side wall of the gate electrode 3 serves to isolate the source and drain regions from each other, making it possible to suppress the gate parasitic capacitance, as described in H. Ishiuchi et al., IEEE Trans. Electron Devices, "Measurement of intrinsic capacitance of lightly doped drain (LDD) MOSFET's" ED-32, P.2238 (1985).
However, the depletion layer formed within the n.sup.- -type region 4 is greater than that formed in the source-drain region of the ordinary structure because the impurity concentration of the region 4 is lower than that of the region of the ordinary structure. The large depletion layer noted above brings about a parasitic drain resistance, with the result that the drain current ID is made lower than that of the region of the ordinary structure even at the initial stage of operation. It follows that the conventional LDD structure shown in FIG. 1 is not satisfactory in the driving capability.